Performance of Dynamically Scheduling VLIW Instructions

compiler to exploit high ILP using EPIC techniques [SI. M-64 processor architecture implementing this concept is the processor architecture where the compiler is responsible for This paper evaluates performance of the Dynamically efficiently exploiting the available ILP and keeps the Inslructian Sch&led KlW P I S w pmcersor mhitechnz. executions busy. Instead of the merits, the IA-64 processor has The DISVLIW processor architecture is designed for performance limitations due to static instruction scheduling and dynamically scheduling VLIW instructions using dependency the difficulty of complicated compiler design. In order to information. Features such as rrplicit parallelirm. balanced overcome c m n t performance bottlenecks in modem scheduling effori, and 4namic scheduling of VLIW architectures, a processor architecture that satisfies the instructions can be used lo provide a sound structure for following criteria is r e q u i d ( I ) balanced scheduling effort supercompufing. We simulate fhe DISvLIW processor between compile time and lun time, (2) dynamic instruction architecture and show that the DISvLIWprocessor p e f o m scheduling, and (3) reducing the size of object code. signfkmtlj befter than the VLlW processor acrass voliour This paper evaluates the ILP processor architecture called numerical benchmark qplications. Dynanucally Instruction Scheduled VLIW (DISVLIW) that achieves these goals. Figure 1 shows a simple diagram of the DISVLIW processor architecture. The DISVLIW processor is